1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method. In particular, the present invention relates to a semiconductor device that includes an insulation layer having a high dielectric constant and its manufacturing method.
2. Background Art
The scale down of CMOS LSIs demand thinner gate insulation layers. Gate insulation layers in the next generation MOS field effect transistors having a size smaller than 0.1 μm are demanded to have equivalent oxide thickness of 1.5 nm or less. In this film thickness region, however, suppression of leakage current caused due to a direct tunnel current cannot be conducted, and SiO2 can no longer be used as a gate insulation layer because of a resultant increase of power dissipation. As a substitute material for it, therefore, a material having a high dielectric constant and a film thickness increased to suppress the leak current, i.e., a high-k material is now being researched and developed vigorously worldwide.
Heretofore, a large number of high-k materials have been proposed. Especially in recent years, for example, a HfO2 layer, a HfSiO layer, or a HfSiON layer obtained by adding N to the HfSiO layer are expected to be promising toward practical use because of not only high dielectric constant but also their thermal stability. Especially, as regards the HfSiON layer, crystallization causing a leak current or impurity diffusion is not caused even after a heat treatment process performed for activation anneal of polycrystalline silicon used as a gate electrode, and an equivalent oxide thickness of 0.6 nm is achieved (see IEDM Tech. Dig. (2003) 107).
In such a structure using a Hf material such as the HfO2, HfSiO or HfSiON layer as the gate insulation layer, a low dielectric constant layer, which is considered to be SiO2 formed by reaction between the gate insulation layer and silicon in the substrate, is formed at an interface between the silicon substrate and the gate insulation layer by heat treatment in a semiconductor device manufacturing process.
Going through the heat treatment in the semiconductor device manufacturing process, silicon in the silicon substrate is diffused in the gate insulation layer and accumulated to the surface of the insulation layer to form silicide and consequently a low dielectric constant layer.
In the generation in which a thinner gate insulation layer having an equivalent oxide thickness of 0.5 nm or less when converted to SiO2 is demanded, presence of such a low dielectric constant layer must be eliminated.
There is not only the problem of presence of the low dielectric constant interface, but also a problem that a ON state threshold voltage at which an MISFET with such a gate insulation layer shifts from its ideal value. This results in a problem that the on-current cannot be ensured in a low power supply voltage state. As for the cause of this threshold shift, it is possible to consider a model in which hafnium is bonded with silicon included in polycrystalline silicon or Si diffused in the substrate at the interface between the polycrystalline silicon electrode and the insulation layer, and the Hf—Si bonding level brings about Fermi level pinning.
These problems of the formation of the low dielectric constant layer and the threshold shift occur not only in the gate insulation layer using the Hf material, but also in a high dielectric constant gate insulation layer using an oxide of Zr, Ti or Ta, which is metal in which silicon in the substrate can be diffused, or metal which can react with polycrystalline silicon serving as the electrode, in the same way.